As Integrated Circuits (ICs) continue to become more advanced, the transistors that are used to construct them continue to decrease in size. Decreases in transistor size create changes in operating specifications associated with smaller transistors. Such changes include decreased operating voltages and tighter common mode voltage tolerances.
One type of device that is affected by decreased operating voltage and tighter common mode voltage tolerances is a charge pump. Charge pumps are fundamental components of many types of devices. For example, a charge pump may be used to adjust the amount of voltage applied to a low pass filter in a phase locked loop. One such charge pump (a differential charge pump) is illustrated in FIG. 1. Charge pump 10 includes a current steerer 12 which is coupled to receive a source current from a current source 14 and a sink current from a current sink 16. The current steerer distributes the source and sink current to output terminals NEG 18 and POS 20. Signals applied to a differential control (differential input terminals 22A-D) may be used to determine a duty cycle associated with the amount of time the source and sink currents are steered to a respective output terminal.
The output terminals 18 and 20 may each be coupled to a capacitor that uses the source and sink currents to charge and discharge. By changing the duty cycle, via the differential inputs 22A-D, the amount of voltage stored on a particular capacitor may be adjusted. For example, if the capacitors are used in a loop filter (in a phase locked loop), the voltage level on each capacitor may be used to differentially control the output frequency of a voltage controlled oscillator.
Because the current steerer 12 is comprised of Field Effect Transistors (FETs) 24-27, decreasing operating voltages (which may be associated with decreasing transistor sizes) have a direct impact on the output current range of current steerer 12. This becomes apparent by examining nodes 28 and 30. The maximum voltage at node 28 and the maximum voltage at node 30 limit the maximum range of output voltage available for input voltages at FETs 24-27. For example, as operating voltages decrease, a larger percentage of an operating voltage intended for FETs 24-27 may be distributed across current source 14 and current sink 16. When this happens less voltage is available for nodes 28 and 30, and as a result, the output current range of current steerer 12 is reduced.
Another shortcoming with current charge pumps is common mode voltage drift. Common mode voltage drift occur when small asymmetries in the charge pump 12 (or asymmetries in the circuit referencing the charge pump) may cause the positive or negative DC voltage across output terminals 18 and 20 to drift to an undesirable voltage level. For example, due to statistical variations that occur in manufacturing (i.e., semiconductor processing), FET 24 may have a smaller channel length (ΔL), channel width (ΔW), and/or threshold voltage (ΔVt) than FET 25. Over time, small differences in current resulting from an asymmetry may cause a capacitor referencing output terminal 20 to store a small increment of charge at each clock cycle. Another capacitor referencing output terminal 18 may not store this increment of charge. A DC voltage, therefore, is established between output terminals and it may grow, or drift, with each clock cycle.
Current charge pumps employ a feedback mechanism that monitors the DC, or common mode, voltage. By monitoring the common mode voltage through a feedback path, and adjusting the charge pump based on the feedback, a feedback mechanism may compensate for the asymmetry. This may be done by adjusting the duty cycle applied to the current steerer 12, for example. Unfortunately, the feedback mechanism increases the complexity of the charge pump and produce additional overhead. The problems associated with asymmetry may also be further exacerbated with decreased transistor sizes.
Therefore there is a need for a charge pump that has an output range that is not restricted by device scaling and processing asymmetries.